Scanning Latches Using Selecting Array

ABSTRACT

A method and system for scanning data from a specific latch in a matrix array of latches. The matrix array is made up of vertical selector lines and horizontal data lines. Each latch is coupled at an intersection of a selector line and a data line by a transistor. By turning on the transistor, the contents of the latch can be selectively read or written to.

PRIORITY CLAIM

The present application is a continuation of U.S. patent applicationSer. No. 10/896,505 (Atty. Docket No. AUS920040243US1), filed on Jul.22, 2004, and entitled, “Scanning Latches Using Selecting Array,” whichis incorporated herein by reference.

CROSS-REFERENCE TO RELATED APPLICATIONS

The parent application is related to U.S. Pat. No. 7,047,468,application Ser. No. 10/670,832, issued on May 16, 2006, andincorporated herein by reference in its entirety.

TECHNICAL FIELD

The present invention relates in general to the field of computers, andin particular to the observation and manipulation of data in stateholding elements. Still more particularly, the present invention relatesto a method and system for reading and writing latch data by selecting aspecific latch through the use of a line selector.

DESCRIPTION OF THE RELATED ART

Computing processor logic is typically made up of multiple clusters ofcombinatorial logic (hereinafter referred to as “logic”) and datalatches. The logic executes machine instructions to manipulate data, andthe data latches store data, including input data being input into logicas well as output data being output from the logic after manipulation. Atypical collection of logic and latches is shown in FIG. 1 a aslogic/latch array 100.

Logic/latch array 100 is made up of multiple state holding elements 102(typically latches) and logics 104. Data bits are input into the topstate holding elements 102 where the data bits are latched, and at asubsequent clock cycle are applied to one or more logics 104. Theresults of the operations of the logics 104 are then outputted to one ormore other state holding elements 102, and so on until the final resultsare outputted at the bottom of the logic/latch array 100. A chip iscomposed of many such blocks of logic and latches.

A common desire when a chip is manufactured is to test whether there areany defects in the manufacturing process that may cause the chip tofunction differently from that which would result from defect freemanufacturing. A test program of data bits (“test vectors”) inputtedinto the top of logic/latch array 100 will output known predictedresults (“result vectors”) from the bottom of the logic/latch array 100after a known number of clock cycles if the logic/latch array 100 isworking properly. However, for a large block of logic, a prohibitivelylarge number of vectors may be required to determine if the logic/latchblock is suitably free from defects. Additionally, the existence offeedback and jumps of data as shown by the arrows in FIG. 1 a mayincrease the number of vectors required to detect all manufacturingdefects, or may make it impossible to detect certain detects. Onesolution to the problem of having a large number of vectors is toindependently check smaller portions of the logic block. This can beaccomplished by setting the state of the internal latches, clocking thesystem, and reading the results from the latches. By checking thesubfunctions between the latches, much smaller numbers of test vectorscan be used to gain higher coverage of the faults.

Thus, to check the accuracy of the operation of logic/latch array 100,interim contents, resulting from operations performed by logics 102, ofstate holding elements 102 are scanned out and inspected. Checking suchintermediate operations and their results utilizes techniques such asLevel-Sensitive Scan Design (LSSD) tests, Generalized Scan Design (GSD)tests, or other scan design test techniques that enable testing at alllevels of VLSI circuit packaging. The principles of the LSSD techniqueare described, for example, in U.S. Pat. No. 3,783,254, U.S. Pat. No.3,784,907 and U.S. Pat. No. 3,961,252, all to Eichelberger andincorporated by reference in their entirety.

FIG. 1 b illustrates latch pairs 106, analogous to the state holdingelements 102 shown in FIG. 1 a, that are used for scanning data out of alatch array 101. Latch pairs 106 hold intermediate results of operationsperformed by logics 104 as described above. (For purposes of clarity,FIG. 1 b omits representations of logics 104 shown and described in FIG.1 a.) To facilitate trustworthy scans, each latch pair 106 illustratedin FIG. 1 b includes a master latch M106 and a slave latch S106. Theslave latches S106 are necessary to ensure that data is not lost throughtiming mishaps that could occur if data bits were to be passed directlyfrom a first master latch to a second master latch.

During a scan-out process, a data bit in a first master latch is firstmoved to a first slave latch, which then passes the data bit to a secondmaster latch, which then passes the data bit to a second slave latch,and so on until the data bit safely passes through the entire latcharray 101. As depicted in FIG. 1 b, the latch array 101 of masterlatches M106 and slave latches S106 is under the clocking control of afirst clock (A_clk) for the master latches M106 and a second clock(B_clk) for the slave latches S106. Thus, when a scan-out operation isperformed, the data bits are scanned out in a serial manner as depicted,wherein the data bit in master latch M106-1 moves to slave latch S106-1,which passes the data bit to master latch M106-2, which passes the databit to slave latch S106-2, and so on until the data bit is finally readout of latch array 101 through/from slave latch S106-x.

Referring now to FIG. 2, there is a block diagram of four master/slavelatch pairs being scanned. Assume in FIG. 2 that instead of twentymaster/slave latch pairs M106/S106, as depicted in FIG. 1 b, there areonly four master/slave latch pairs M106-1/S106-1 through M106-4/S106-4in a First-In First Out (FIFO) 206, as depicted. At initial time “T1”,input queue 208 holds data elements “w, x, y, z,” each master latch M106holds a significant data bit (such as a result of an intermediateoperations performed by some piece of logic), each slave latch S106 isempty or in a “don't care” state, and the output queue 210 is empty (orin a “don't care state). At time “T2”, all the data bits are shiftedinto the available slave latches. Thus, data bit “A” moves from masterlatch M106-1 to slave latch S106-1, data bit “B” moves from master latchM106-2 to slave latch S106-2, data bit “C” moves from master latchM106-3 to slave latch S106-3, and data bit “D” moves from master latchM106-4 to slave latch S106-4.

Moving on to time “T3”, the data bits are shifted into the masterlatches either from slave latches or from the external queue. Inaddition a data bit will be shifted to the output queue. So, data bit“z” from input queue 208 shifts into master latch M106-1, data bit “A”advances from slave latch S106-1 into master latch M106-2, data bit “B”advances from slave latch S106-2 into master latch M106-3, data bit “C”advances from slave latch S106-3 into master latch M106-4, and data bit“D” advances from slave latch S106-4 into output queue 210. (Note thatinput queue 208 and output queue 210 may also have master/slave latchpairs (not shown) as depicted for FIFO 206.)

Continuing along the time line in FIG. 2, significant data bits arecontinued to be scanned out of FIFO 206 until time “T9”, at which timeall of the leading data bits (w, x, y, z) originally in input queue 208are scanned into FIFO 206, and all of the significant data bits (A, B,C, D) are scanned out of FIFO 206 into output queue 210.

One significant limitation of the traditional scan chain described inFIGS. 1 a-b and FIG. 2 is that all data in the scan chain must bescanned out in a serial manner. Thus, to view a specific scan chainlatch, the entire scan chain must be scanned out, and the contents of aspecific scan chain latch must be “picked out” as it enters the outputqueue 210 shown in FIG. 2.

Another limitation of traditional scan chains is that they require theadditional slave latches S106 to ensure accurate serial movement throughthe serial pathway shown in FIG. 1 b. Although additional latches arenot needed when a logic/latch block stores internal states inmaster-slave flip-flips, which themselves are pairs of master and slavelatches, slave latches S106 are necessary if mid-cycle latches scheme isused, in which data is latched into a first latch on a clock signalrise, and then latched into a second latch on the same clock signal'sfall.

Thus, it would be a useful improvement of the prior art to have a systemthat allows a specific latch to be directly accessed, allowing theexamination of the contents of only that specific latch, without addingadditional storage elements to the system.

SUMMARY OF THE INVENTION

The present invention is therefore directed to a method and system fordirectly accessing internal data from a specific latch in a matrix arrayof latches. The matrix array includes vertical selector lines andhorizontal data lines. Each latch is coupled at an intersection of aselector line and a data line by a transistor. By turning on thetransistor, the contents of each latch can be selectively accessed.

Each latch in a single column selected by a selector line puts a high orlow signal (binary data) on one of the data lines. The data on each ofthe data lines is then amplified by a sense-amplifier that senseswhether the data on each data line is high or low. The data on the datalines is sent to an output buffer, and then to a computer, where thedata (i.e., contents of the latches) can be examined.

Alternatively, each latch in a column can be individually accessed usinga “write transistor” to write data from a data line to a latch, and adifferent “read transistor” to read data to the data line from the samelatch.

Alternatively, data can be read from particular latches by pre-chargingthe data lines, and then reading the contents of a column of latches bycoupling each latch in the column to a respective data line.

The above, as well as additional objectives, features, and advantages ofthe present invention will become apparent in the following detailedwritten description.

BRIEF DESCRIPTION OF THE DRAWINGS

The novel features believed characteristic of the invention are setforth in the appended claims. The invention itself, however, as well asa preferred mode of use, further objects and advantages thereof, willbest be understood by reference to the following detailed description ofan illustrative embodiment when read in conjunction with theaccompanying drawings, where:

FIG. 1 a depicts a prior art logic/latch array of state holding elementsand processing logic;

FIG. 1 b illustrates a prior art array of state holding elements havingdata sequentially scanned out;

FIG. 2 depicts a single row of state holding elements having datascanned out using prior art master/slave latch pairs;

FIG. 3 a illustrates a 2×2 matrix of latches that can be read from orwritten to using a line selector and an input/output (I/O) buffer;

FIG. 3 b depicts a decoder used by the circuit illustrated in FIG. 3 aand FIG. 5 to place a signal on a specified select line;

FIG. 4 a illustrates a 2×2 matrix of latches that can read and writedata to the latches using separate read and write select lines;

FIG. 4 b depicts a decoder used by the circuit illustrated in FIG. 4 ato place a signal on a specified select line; and

FIG. 5 illustrates a 2×2 matrix of latches that can read data fromlatches using data line pre-chargers.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

With reference now to FIG. 3 a, there is depicted a preferred embodimentof the present invention for reading and writing data from latches.Depicted is a matrix 300, which is a 2×2 matrix of four state holdingelements shown in exemplary form as latches 302-1 to 4. Only a 2×2matrix is shown for purposes of clarity, but it is understood that scanmatrix 300 may contain hundreds, thousands, or more latches 302.

Each latch 302 is coupled to a data line 304 via an NFET (N-type FieldEffect Transistor). For example, latch 302-1 is coupled to data line304-a via NFET 306-1. Data lines 304 are coupled to an output scanstorage unit shown as an Input/Output (I/O) buffer 308, which is a databuffer for data being written to or read from the latches 302. Consideras an example of usage of the present invention the steps taken to readdata from exemplary latch 302-1.

First a read/write block 310-a is switched to a “Read mode” to allowdata on data line 304-a to be sensed, and then to amplify that data fortransmission to and storage in a specific latch (not shown) in I/Obuffer 308. Also, a “Read Signal” is set high in the I/O buffer 308,allowing data from data line 304-a to be stored in a specific latch (notshown) in I/O buffer 308. Additionally, a line selecting signal isreceived in a line selector 312, which using circuitry shown in detailin FIG. 3 b, causes a select line 314-a to go high (positive voltagerepresenting a logic 1), thus turning on NFET 306-1. If latch 302-1 isholding a “0”, then a “0” (low voltage) is put on data line 304-a.Conversely, if latch 302-1 is holding a “1”, then NFET 306-1 allows apositive voltage charge to be put on data line 304-a. The content ofdata line 304-a (high or low: “1” or “0”) is then sensed and amplifiedby read/write block 310-a, and that data is then stored in I/O buffer308.

The latch data copied to the I/O buffer 308 can be read using a normalLSSD scanning technique. That is, by alternatively setting “A Clk” and“B Clk” to high, the data stored in the I/O buffer is read sequentiallyfrom the “Output” port of I/O buffer 308. The internal structure of I/Obuffer 308 is clear to those skilled in the art of LSSD scan technique.

In order to read all the data stored in all the latches, data can beread column by column. For example, all the latch contents in FIG. 3 acan be read by first setting the selector signal 314-a to copy the latchvalues of latch 302-1 and latch 302-3 into the I/O buffer 308, thentransferring the contents of the I/O buffer using the above mentionedtechnique to an external device such as a computer, then setting theselector signal 314-b to copy the latch values of latch 302-2 and latch302-4 into the I/O buffer, and then transferring those values from theI/O buffer 308 to the external device.

With reference now to FIG. 3 b, additional detail is shown for preferredcircuitry used to select a particular select line 314. A decoder 316 inline selector 312 (shown in FIG. 3 a) receives a line selecting signal.Decoder 316 is able to take the line selector signal input on “n” inputlines to cause one of 2^(n) select lines 314-a, b, x or n to ultimatelygo high. (Select lines 314 x and n are for other columns of latches 302that are not shown in FIG. 3 a).

Assume that the line selecting signal shown in FIG. 3 b is input on twolines (n=2). Using binary math, this allows four binary values (00, 01,10, 11) to be input and decoded. If the input on the two lines is01_(bin), then output line “01” being input into an AND gate 318-a willbe high. If the clock signal is also high, then the output of AND gate318-a and only 318-a will be high, making select line 314-a the onlyhigh select line. (Note that voltage control components 324 areoptional, and may be used to control the slew rate of NFETs 306 in amanner described below. If voltage control components 324 are notpresent, then select lines 314 are output directly from AND gates 318.)

Next, consider steps taken when writing data to exemplary latch 302-1 asshown in FIG. 3 a.

First, data to be written is shifted into the I/O buffer by the LSSDscan technique, toggling the A Clk and B Clk. Then, the read/write block310-a is switched to a “Write mode” to allow the stored data from alatch (not shown) in I/O buffer 308 to be put on data line 304-a. Then,a line selecting signal is received in line selector 312, which usingcircuitry shown in FIG. 3 b, causes select line 314-a to go high(positive voltage representing a logic 1), thus turning on NFET 306-1.The content of data line 304-a is then stored in latch 302-1.

In order to use to use the same NFET 306 to either read or write data toa latch 302, different methods can be used. For the purpose of example,consider reading or writing data to latch 302-1. One method ofselectively reading or writing this data is to vary the slew rate ofNFET 306-1. By having a slow slew rate (gradually turning NFET 306-1),then the content of latch 302-1 will be allowed to be slowly put on dataline 304-a, preventing the charge in the data line 304-a from disturbingthe value in the latch 302-1. Alternatively, by having an high slew rate(quickly turning on NFET 306-1), the charge stored in the data-linesuddenly rushes into the latch 302-1, overwriting the data-stored in thelatch. The slew rate is controlled by voltage control components 324shown in FIG. 3 b in a manner understood by those skilled in the art ofelectronics.

Similarly, a threshold voltage level of NFET 306-1 can be manipulated toallow data to be read or written to latch 302-1. If a control voltage onNFET 306-1 is maintained in a middle range (such that NFET 306-1 is onlypartially turned on), the data in the latch slowly changes the value inthe data-line 304-a, resulting in a read operation. Conversely, if thecontrol voltage of NFET 306-1 is such that NFET 306-1 is turned fullyon, then the contents of data line 304-a are forced into latch 302-1,resulting in a write operation.

Alternatively, a voltage difference in latch 302-1 and data line 304-acan result in NFET 306-1 being used to permit a write operation to latch302-1. Thus, using latch 302-1 as an example, assume that thetransistors in latch 302-1 are tied to a supply voltage identified asV₁. Putting on data line 304-a a voltage V₂ that is positively higherthat V₁ represents a “1” on data line 304-a. Since V₁ is much greater(more positive) than V₂, then the “1” on data line 304-a will be forcedinto (written to) latch 302-1. Similarly, putting a voltage V₃ on dataline 304-a that is much less (more negative) than V₁ represents a “0” ondata line 304-a. Since V₃ is much more negative than V₁, then any chargein latch 302-1 will be pushed onto data line 304-a, resulting in a “0”being written to latch 302-1.

The steps for reading or writing to other latches 302 shown in FIG. 3 aare the same as described above with respect to latch 302-1.

With reference now to FIG. 4 a, there is illustrated an alternatepreferred embodiment of the latch read/write circuitry shown in FIG. 3a. The difference in FIG. 4 a is that instead of a same select line 314regardless of whether data is to be read or written to a latch 302, eachcolumn of latches 302 have different read select lines 402 and writeselect lines 404 that are selected by a line selector 402 having adecoder 408. The read select lines 402 and write select lines 404 arecoupled to separate Field Effect Transistors (FETs), identified as ReadFETs (RFETs) and Write FETs (WFETs). Thus, the function of the singleFETs 306 shown in FIG. 3 a is broken out into separate RFETs and WFETs.

The choice of whether a read or write operation is to be performeddepends on the value of the Read/Write signal coming into line selector402. Note that the function of read/write blocks 310 and I/O buffer 308is similar to that described above for FIG. 3 a, and will not bereiterated here.

Preferably, RFETs are small transistors similar to those used ininverter 322-1 small, and the WFETs are large transistors similar tothose found in inverters 322-2 large, both inverters making up latch302-1. Thus, when a WFET is turned on, its brute power allows it toovercome any push-back from inverter 322-1 small, resulting in a writeoperation to the latch 302-1. Similarly, when an RFET is turned on, itoffers little resistance to inverter 322-2 large, resulting in datapassing from latch 302-1 to data line 304 for a read operation.

Referring now to FIG. 4 b, the selection of a read or write select linedepends on the input of the line selecting signal as well as theRead/Write signal coming into the decoder 408. Consider as an examplethe events that occur if data is to be read from latch 302-1. Assumethat line selecting signal is on a single line (n=1). Assume also that asignal of “0” on the Read/Write signal means “read,” and a signal of “1”on the Read/Write signal means “write.” To put read select line 402-ahigh, then the input on the single line selecting signal is “1,” and theinput on the read/write signal is “0.” These inputs cause the linecorresponding to the “10” output to go high. The line from the “10”output is logically ANDed with a high clock signal in AND gate 406-2 toproduce a high signal on read select line 402-a. Similarly, if data isto be written from latch 302-1, then a signal of “1” is input as theline selecting signal, and a signal of “1” is input as the Read/Writesignal, thus causing the line from the output labeled “11” to go high.When this line is logically ANDed with a high clock signal in AND gate406-1, then write select line 404-a goes high.

While terms such as “high” and “low” have been used in an exemplarymanner to describe logical “1” and “0” respectively, it is understoodthat alternate logical values may be used by altering circuitry (such assubstituting PFETs for NFETs) to achieve a same logical result.Likewise, the AND gates 318 and 406, shown respectively in FIGS. 3 b and4 b, may be NAND, OR, NOR or other logical units with minimal alterationof the circuitry.

Referring now to FIG. 5, a matrix 500 is depicted that is similar tomatrix 300 depicted in FIG. 3 a, except that matrix 500 can only readdata from latches 302. Data is read from pre-charged data lines 304,which are pre-charged using pre-chargers 502. Steps taken to read datafrom latches 302 shown in FIG. 5 are as follows. First, data lines 304are pre-charged with a “1” signal upon a low clock signal being inputinto line selector 302 and a PFET in each pre-charger 502. The lowsignal turns on each PFET, allowing each data line 304 to be coupled toV_(dd). Since line selector 312 uses the same decoder 304 and circuitrydescribed in FIG. 3 b, none of the read select lines 314 have a readsignal (high) on the line.

When the clock signal then goes high, the PFETs in the pre-chargers 502are turned off, thus isolating the data lines 304 from V_(dd). Afterturning on a select line 314, data latched in selected latches 302 isthen sensed on a data line 304 and amplified by read blocks 504. Thedata is then sent to an Output buffer 506.

Consider an example of reading a “0” from latch 302-1. Afterpre-charging data line 304-a using pre-charger 502-a, a high Read signal“1” is put on select line 314-a. This high signal turns NFET-1 a on.Since latch 302-1 is outputting a “0,” then NFET-1 b (acting as adischarge switch to data line 304-a) is turned off, thus blocking apathway from data line 304-a to ground. Therefore, data line 304-a willstill have a charge, indicative of a “1,” which is the inverse of thetrue content of latch 302-1. Therefore, an inverter 508-a is locatedbetween read block 504-a and Output buffer 506, resulting in a correctvalue of “0” being stored in Output buffer 506. (To rectify the valueread out of latch 302-1, the value can alternately be inverted usingsoftware.)

Now consider reading a “1” from latch 302-1. After pre-charging dataline 304-a using pre-charger 502-a, a high Read signal “1” is put onselect line 314-a. As before, this high signal turns NFET-1 a on, butnow, since latch 302-1 is outputting a “1,”, then NFET-1 b is turned on,thus allowing NFET-1 b to act as a discharge switch to discharge dataline 304-a. As data line 304-a now has no charge, indicative of a “0,”then inverter 508-a (or alternatively, software) inverts this value to a“1,” thus representing the true content of latch 302-1.

An advantage of the system shown in FIG. 5 is that there is no “bounce”on data lines 304, and thus the length of data lines 304 is of little orno consequence in the operation of the scan system. A disadvantage ofthe system shown in FIG. 5, however, is that the charge on data lines304 must be captured by Output buffer 506 before the charge on the datalines 314 bleeds off from errant pathways. Another, and perhaps moresignificant, disadvantage is that data can only be read from, and notwritten to, the latches 302.

While the line selectors 312 in the preceding figures have been depictedusing a multiplexer (MUX) decoder 304, alternatively select lines can beset high (or low) using a shift register (not shown). That is, eachexternal scan clock signal going into scan clock generator can result ina different individual select line going high, usually in a sequentialmanner. Thus, in FIG. 3 b, a first external scan clock signal causesselect line 314-b to go high, a second external scan clock signal causesselect line 314-a to go high, and so on for other select lines 314-x andthen 314-n.

Whichever method is used to cause a select line to go high, preferablyonly a single select line can be set high while all other select linesremain low. This allows a specific column of latches to be selected.When a specific column of latches is selected by a read signal on aselect line, the contents of some or all of those latches can becaptured by the output buffer.

For purposes of clarity, each state holding element has been describedas a latch. Note however that these state holding elements may be anyholding element capable of holding scan data. Such state holdingelements may be flip-flops, registers, or any other similar stateholding element. Further, the state holding elements may simply be awire, capacitor, or other physical device charged or discharged toreflect a logic state.

Note also that for purposes of clarity, the latches 302 are depicted in2×2 matrices of horizontal rows and vertical columns. While thisorientation is referenced in the specification and associated claims, itis understood that the orientation is not limited by Cartesiandirections such as horizontal and vertical or rows and column. Thus, areference to a “horizontal” array or a “row” is only to distinguish anarray of latches 302 in their coupling to a single data line whencompared to latches in a “vertical” array or “column” coupled to asingle select line. Note also that the 2×2 size of the matrices is forpurposes of illustration only, as it is understood that the size of thematrices is preferably much larger than 2×2.

While individual switches are depicted as various FETs (NFETs andPFETs), it is understood that any similar switching device may be used,including BJTs and other similar switches, so long as signal areadjusted accordingly to turn the switches on and off in the mannerdescribed above.

The present invention, as described in its preferred embodiment, is thusable to scan data out of latches with greatly increased granularity,including immediately selecting a single latch within a latch matrix(array). Furthermore, since each latch can be directly accessed, thedata jam shown in FIG. 2 is also avoided. Note that this data jam can beavoided both in the scan direction as well as the data flow direction,as is also the case of the system and method described in co-pendingU.S. patent application Ser. No. 10/670,832.

It should be understood that at least some aspects of the presentinvention may be implemented in a program product. Programs definingfunctions on the present invention can be delivered to a data storagesystem or a computer system via a variety of signal-bearing media, whichinclude, without limitation, non-writable storage media (e.g., CD-ROM),writable storage media (e.g., a floppy diskette, hard disk drive,read/write CD ROM, optical media), and communication media, such ascomputer and telephone networks including Ethernet. It should beunderstood, therefore in such single-bearing media when carrying orencoding computer readable instructions that direct method functions inthe present invention, represent alternative embodiments of the presentinvention. Further, it is understood that the present invention may beimplemented by a system having means in the form of hardware, software,or a combination of software and hardware as described herein or theirequivalent.

While the invention has been particularly shown and described withreference to a preferred embodiment, it will be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the spirit and scope of the invention.

1. A system for accessing data from multiple latches, the systemcomprising: multiple data flow paths composed of multiple latches havingintervening logic circuits, the latches functionally composed of holdingdevices for logic circuit data; selective interconnects coupling latchesin different data flow paths of the multiple data flow paths; and a dataaccessing matrix coupled to two or more latches in two or more data flowpaths by switching devices, the switching devices being activated by aline selector that activates the switching devices along a column of thedata accessing matrix, wherein the contents of all latches in the columnare output to multiple data lines along rows of the data accessingmatrix.
 2. The system of claim 1, further comprising: means forselecting one of the data line rows of the data accessing matrix.
 3. Thesystem of claim 1, further comprising: an input/output (I/O) buffercoupled to the data lines, wherein data read from the latches istransmitted via the data lines to the I/O buffer.
 4. The system of claim1, wherein each of the latches is composed of feedback coupledinverters.
 5. The system of claim 1, wherein the switching devices aretransistors.
 6. The system of claim 1, further comprising: a pre-chargercoupled to each data line; and a separate discharge switch coupling eachof the latches to ground, wherein if a latch holds a first logicalvalue, then the data line that is coupled to that latch is discharged,and wherein if that latch holds a second logical value, then the dataline coupled to that latch remains charged.
 7. The system of claim 1,further comprising: at least one read select line and at least one writeselect line coupled to a line selector; a read switch controlled by oneof the read select lines, the read switch coupling one of the latches toone of the data lines; and a write switch controlled by one of the writeselect lines, the write switch coupling the same one of the latches tothe same one of the data lines, wherein data is read from the latch tothe data line by closing the read switch while the write switch is open,and wherein data is written from the data line to the latch by closingthe write switch while the read switch is open.